Published Oct. 28, 2025
Summary
This technology uses superconducting electronics with unary SFQ pulse circuits to create a neural network for ultra-fast quantum state discrimination, significantly reducing latency in hybrid quantum-classical systems.
Applications
- Quantum computing
- Quantum sensors
Benefits
- 10X less latency than state-of-the-art latency quantum state discrimination, enabling real-time quantum-classical feedback and error correction
- Energy-efficient superconducting electronics with extremely low energy dissipation per pulse
Background
Several algorithms such as Variational Quantum Eigensolver (VQE) or Quantum Error Correction (QEC) combine classical and quantum algorithms to leverage the computing capabilities of near-term noisy intermediate scale qubits (NiSQ). The classical part of the algorithm runs on room temperature electronics for pre/post-processing of the input/output of the quantum processing unit (QPU). Although these classical-quantum algorithms are promising for the NiSQ era, one bottleneck is the slow communication channel between the QPU, inside a cryostat, and the classical hardware (CPU, GPU, FPGA) at room temperature. In fact, measuring, transmitting, and processing the qubit output with room temperature electronics takes +1ms, that is 100X more than the coherence time of a qubit (400ns-1us), creating significant latency issues. Solutions are needed to minimize the latency of measuring, transmitting, and processing the qubit output.
Technology Description
Scientists at Berkeley Lab have developed a classical superconducting accelerator capable of performing qubit manipulation, readout, and classical computation for large scale quantum computers. Leveraging the ultra low energy and super fast frequency of operation (50GHz) of superconducting electronics, they developed a superconducting quantum state discriminator that uses SFQ digital and analog gates to make computation energy efficient and minimizing latency issues in hybrid quantum-classical systems.
It uses unary data encoding to enable minimum footprint computing elements. This technology enables placing the quantum state discrimination hardware inside the cryogenic refrigerator at 4K, a significant advantage over cryo-CMOS and CMOS counterparts because it not only reduces wiring complexity but also enables minimum computing latency. The architecture has achieved latencies as low as 4.32 ns for single-shot discrimination with 4-bit resolution.
Development Stage
TRL 3: Proof of concept
Inventors
IP Status
Patent pending
Opportunities
Available for licensing or collaborative research
