Quantum Computing and Related Technologies

Multiplex Noise Engineering and Qubit Control to Address Two-Level System Defects (2025-068)

An invention which uses a DC electric field to spectrally tune these TLS defects away from the qubit transition frequency, mitigating their detrimental effects on qubit performance. Conventionally, adding DC electrodes involves a separate structure from the qubit control wiring and adds overhead onto a large-scale quantum processor. This invention combines DC electrode and RF qubit control in a single structure that enables both TLS and qubit control.

Inventors: Larry Chen, Kan-Heng Lee

Ultra-Fast, Low-Latency Quantum State Discrimination for a Cryogenic Environment (2025-060)

This technology uses superconducting electronics with unary SFQ pulse circuits to create a neural network for ultra-fast quantum state discrimination, significantly reducing latency in hybrid quantum-classical systems.

Inventors: Luisa Gonzalez, Anastasia Butko, Meriam Bautista

Protocol for Computing Polynomial on Quantum State (2024-155)

Scientists at Berkeley Lab have developed the EHands algorithm, a constructive method for computing d-degree polynomials on a quantum computing unit (QPU). This algorithm encodes real values onto quantum states and utilizes four specific quantum operations: addition, multiplication, negation, and parity flip. EHands has the potential to significantly enhance the efficiency of tasks involving transformations of higher-dimensional data, such as quantum optimization, machine learning, financial modeling, and scientific simulation. 

Inventors: Jan Balewski, Roel Van Beeumen

FPGA-based In-Situ Machine Learning for Real-time Quantum State Discrimination (2024-145)

This technology enables real-time quantum state discrimination on field programmable gate array (FPGA) hardware by integrating a multi-layer neural network onto an RFSoC platform, eliminating the latency and errors associated with transferring quantum data to host computers for processing, and achieving precise and rapid computation. Provides feedback and verification of quantum states, offering a robust and scalable solution for real-time quantum computing applications that surpasses existing methods limited by latency and state discrimination capabilities.

Inventors: Yilun Xu, Neel Vora, Gang Huang, Phuc Nguyen

Superconducting Tsetlin Machines for Efficient Deep Neural Networks (2024-078)

A novel implementation of the Tsetlin machine using superconducting rapid single-flux quantum (RSFQ) technology. This innovation combines the interpretability and efficiency of Tsetlin machines with the ultra-low power consumption and high processing speeds of superconducting circuits, potentially revolutionizing energy-efficient, high-speed computing for machine learning applications.

Inventors: Dilip Vasudevan, Ran Cheng, Christoph Kirst

Hardware-Assisted Parameterized Quantum Circuit Execution (2024-074)

A new technique for improving the efficiency of quantum circuit execution, called Hardware-assisted parameterized execution. This approach identifies and selectively compiles structurally-similar circuits from a batch of circuits, separates the quantum circuits from their parameters in the classical computer, and re-attaches them while executing on the control system hardware. This technique significantly reduces compilation time and adds minimal runtime overhead on resource-constrained control systems.

Inventors: Abhi Rajagopala, Neelay Fruitwala, Akel Hashim, Kasra Nowrouzi, Gang Huang, Yilun Xu, Irfan Siddiqi

Hardware Efficient Randomized Compiling for Quantum Computing (2024-053)

A hardware efficient protocol for performing randomized compiling (RC). The new method implements RC directly on the Field Programmable Gate Array (FPGA) within the qubit control system. The FPGA generates the randomized operations and correction gates during the execution of the quantum circuit, eliminating the need to perform these steps in software. The method has zero runtime overhead for most single-qubit gate implementations, and negligible compile time overhead, reducing the overall time complexity of compilation significantly. The increase in speed is about 250 times faster than standard state of the art systems.

Inventors: Gang Huang, Neelay Fruitwala, Akel Hashim, Yilun Xu, Abhi Rajagopala, Ravi Naik, Kasra Nowrouzi, Irfan Siddiqi

RSFQ Multiple Output Toggle Flip Flop for Area Efficient Superconducting Digital Computing (2023-037)

This invention is a multi-output TFF (True/False Flip-Flop) design that reduces the area, power, and latency of multiple types of compute and memory circuits by replacing circuits with tens of cells, leading to a TFF capable of more than two outputs.

Inventors: Meriam Gay Bautista, George Michelogiannakis, Darren Lyles, Patricia Gonzalez-Guerrero

Superconducting-Oscillatory Neural Network with Pixel Error Detection for Image Recognition (2023-028)

A superconducting oscillatory neural network (ONN) for image recognition, leveraging rapid single flux quantum (RSFQ) technology. This innovative system features inductively coupled ring oscillators based on Josephson junctions, which operate at frequencies up to tens of GHz (significantly faster than CMOS) while consuming only a few attojoules per operation, significantly less than CMOS systems. 

Inventor: Dilip Vasudevan

Efficient Temporal Arithmetic Logic Design for Faster Superconducting RSFQ Logic (2023-027)

An approach to designing multiplication circuits, focused on reducing the complexity and improving the efficiency of these circuits. By integrating digital-to-time and time-to-digital conversion into the logic of the circuit and representing signals as decimal values instead of binary values, the approach reduces the need for additional interface circuits and minimizes the number of time delays required to represent numerical values. Particularly beneficial for larger-scale multiplication operations, such as those involved in Fast Fourier Transforms. 

Inventors: Dilip Vasudevan, Georgios Michelogiannakis

RRAM-Based FPCA Architecture for Flexible and Efficient Higher Performance Computing (2023-094)

A memory-centric, reconfigurable, general-purpose computing platform capable of performing analog, digital, and memory functions while efficiently handling explosive amounts of data and performance bottlenecks. The architecture utilizes reprogrammable FPCA with crossbar layouts designed for efficient and massively parallel computing and data storage tasks. 

Inventors: Hasita Veluri, Dilip Vasudevan

An Area-efficient Superconducting Unary Convolutional Neural Network (CNN) Accelerator for High Performance Computing Systems (2022-056)

This invention is a new approach to hardware acceleration for convolutional neural networks (CNNs) using superconducting chips. It leverages innovative race logic and pulse streams as the computational model foundation, significantly enhancing CNN computations’ efficiency.

Inventors: Patricia Gonzalez-Guerrero, Georgios Michelogiannakis

Packet-Switched Superconducting Temporal Network Operations Center (NoC)  (2022-030)

A network-on-chip (NoC) for superconducting digital computing that operates using race logic, a temporal data representation model. The dynamic nature of the on-chip network matches the pattern of incoming traffic well and does not have to force it to fit a schedule like other NoCs do. In addition, circuits that operate in the temporal domain are not forced to convert between binary and temporal data in order to use traditional binary NoCs, enabling more efficient scale-up of temporal computing systems. That said, this NoC does not restrict data representation since packets can be interpreted as race logic, binary, or other forms of data, allowing application to many different systems. This network is also physically smaller than existing NoCs, so it offers higher data throughput per area than competing options.

Inventors: Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Bautista, George Michelogiannakis

Unary Single Flux Quantum (U-SFQ) Architecture for Scaling Superconducting Accelerators (2021-112)

This invention is the Unary Single Flux Quantum (U-SFQ) architecture, which utilizes pulse-streams and Race Logic (RL) to overcome the area constraints and complex architectures that limit current superconducting prototypes. Compared to current binary-based superconducting circuits, U-SFQ processes information up to 200 times more efficiently, requiring significantly fewer Josephson Junctions (JJs) and offering enhanced accuracy in noisy environments.

Inventors: Meriam Gay Bautista, Luisa Patricia Gonzalez-Guerrero, Darren Lyles, Georgios Michelogiannakis

Quantum Instruction Set Architecture (QUASAR) (2021-061)

QUASAR, Quantum Instruction Set Architecture, is a software hardware interface for quantum computing. This facilitates a well-defined interface between quantum circuit software and hardware gate generation.

Inventor: Anastasiia Butko

A Novel Design Method for On-Chip Superconducting Networks Using Race Logic (2021-009)

This invention is a novel design methodology enabling the creation of on-chip networks utilizing race logic, a time-domain computational model not previously utilized in network designs. By leveraging race logic’s manipulation of signal delays instead of binary encoding, this technology achieves significantly higher performance in superconducting circuits.

Inventors: Georgios Michelogiannakis, Darren Lyles, Dilip Vasusdevan, Patricia Gonzalez-Guerrero, Meriam Bautista.

A Superconducting Quantum Processor Unit – A More Efficient Architecture for Quantum Computing (2020-121)

This invention integrates the controllability of superconducting circuits with programmable, all-to-all reconfigurable qubit connectivity, enabling the exploration and demonstration of various Noisy Intermediate-Scale Quantum (NISQ)-era quantum applications at scale.

Inventors: Irfan Siddiqi, Jie Luo, Brian Marinelli

A New Design for RSFQ Superconducting Logic Computation Systems (2020-015)

This invention merges superconducting logic, temporal predicate logic, and delay-based codes to design temporal logic computation primitives in rapid single flux quantum (RSFQ) superconducting logic. By introducing a new data-driven-self timed scheme (DDST), clock distribution overhead in traditional RSFQ logic cells is significantly reduced.

Inventors: Dilip Vasudevan, Georgios Michelogiannakis, John Shalf

Quantum Materials

Low-phonon-energy Nanoparticles for Optical Imaging and Electronics (2023-018)

This invention is a novel class of low-phonon-energy nanoparticles, comprising lanthanide-doped alkali metal halides. These nanoparticles offer environmental stability, efficient doping with lighter lanthanides, and ultra-low phonon energies, enabling sub-wavelength resolution imaging (<100 nm) and optimization of various properties such as quantum yield, spectral purity, and coherence times.

Inventors: Zhuolei Zhang, Artiom Skripka, P. James Schuck, Bruce Cohen, Emory Chan

Supramolecular Assembly of Halide Perovskite Blue Emitter for High-Yield, Tunable Optoelectronics (2022-127)

This invention is a method to stabilize the emission centers of halide perovskite components widely used in optoelectronics and lighting. These supramolecular assembled solids offer highly tunable emission colors, cost-effective synthesis in polar organic solvents at 80°C, and enhanced air stability compared to traditional vacancy-ordered double perovskites, making them promising for various applications.

Inventors: Peidong Yang, Cheng Zhu

Scalable Quantum Computer Architecture with Coupled Donor-Quantum Dot Qubits (IB-3140)

This quantum computing architecture employs single spin memory donor atoms embedded in a semiconductor layer, along with quantum dots arranged and aligned with these donor atoms. By applying voltages across aligned pairs of quantum dots and donor atoms, the coupling between them is controlled, enabling quantum computing operations.

Inventors: Jeffrey Bokor, Cheuk Chi Lo, Stephen Lyon, Thomas Schenkel, Alexei Tyryshkin, Christoph D Weis

Tunable Graphene Electronic Devices (JIB-2697)

This invention introduces a method to induce two-dimensional superconductivity in graphene sheets and adjust their material characteristics using an electrostatic gate. By leveraging the electric-field effect of graphene, the coupling between order parameter inducing islands can be modified, offering a simpler alternative to traditional methods requiring changes in material composition or pressure. This approach enables precise control over the properties of electronic devices, facilitating applications such as photoelectric characteristics, chemical specificity, spintronics, and superconductivity.

Inventors: Jeffrey Bokor, Cheuk Chi Lo, Stephen Lyon, Thomas Schenkel, Alexei Tyryshkin, Christoph D Weis