APPLICATIONS OF TECHNOLOGY:
- Advanced Materials: Semiconductors/PV
- Enables maintenance of high electronic performance
- Generates single crystal domains
- Circumvents substrate costs
- Reduces system and design complexity
Three-dimensional integration of microelectronic circuits – where additional devices are placed above prior layers in the overall structure – is a promising approach for increasing device density in electronics as size scaling approaches physical limits. However, all thin-film growth methods have been limited to temperatures well above the ~400°C thermal budget for silicon integrated circuits (ICs). To address this issue, researchers at the Berkeley Lab have developed a novel templated liquid phase (TLP) growth method to lower sample growth temperatures to below 300°C.
This TLP growth method improves III-V growth compatibility with a large variety of materials (e.g., silicon ICs, transparent conductive glasses, some plastics) and enables direct growth on amorphous substrates. The method uses a carefully controlled thermal gradient to separate the precursor cracking step from the deposition step. Precursor cracking generally requires higher temperatures than most materials and substrates can tolerate so separating the steps allows for optimal, different temperatures for both. The present technology has shown impressive results, as it is capable of extending the growth to substrate temperatures as low as 180°C. In addition, light emitting devices and promising transistor structures have been demonstrated at 270°C and 370°C, respectively.
III-V materials are especially attractive due to their high-performance properties but have been the most challenging to grow directly by alternate methods. The key application of this invention is the further advancement of the semiconductor industry, as the many years of “Moore’s Law” will come to an end in the near future without alternative methods for increasing transistor density or performance. As this method offers a direct III-V materials growth option with a traditional bottom-up fabrication scheme that is thermally compatible with all existing circuit structures, given sufficient maturation the technology has the potential to be present in all microelectronic structures and products moving forward.
DEVELOPMENT STAGE: Proven principle
STATUS: Patent pending. Available for licensing or collaborative research.
SEE THESE OTHER BERKELEY LAB TECHNOLOGIES IN THIS FIELD:
Direct Growth of Single Crystalline III-V Semiconductors on Amorphous Substrates 2016-037