APPLICATIONS OF TECHNOLOGY:
Any application where efficient and high-performance multiplication operations are required, such as:
- Digital signal processing
- Scientific computing
- Communication systems
- Machine learning/artificial intelligence systems
BENEFITS:
- Faster operations
- Lower area requirements
- Dense computation capabilities
BACKGROUND:
In modern digital systems, multiplication circuits are essential components of processors, digital signal processors (DSPs), and other integrated circuits where arithmetic operations are required. Traditional multiplication circuits, especially those based on binary multiplication algorithms, can be slow, resource intensive in terms of area requirements and power consumption, and have limited scalability. In contrast, temporal multiplication utilizes digital-to-time and time-to-digital conversion and temporal representation of signals to achieve significant improvements in performance, power consumption, and chip area compared to traditional binary multiplication methods.
TECHNOLOGY OVERVIEW:
Scientists at Berkeley have created an approach to designing multiplication circuits, focused on reducing the complexity and improving the efficiency of these circuits. By integrating digital-to-time and time-to-digital conversion into the logic of the circuit and representing signals as decimal values instead of binary values, embodiments reduce the need for additional interface circuits and minimize the number of time delays required to represent numerical values. This results in a more streamlined and efficient multiplication process, with fewer clock cycles needed to compute products.
Additionally, embodiments include new multiplier designs that leverage the temporal representation of signals to reduce the total number of input/output signals needed, further reducing area footprint and power consumption on the chip.
Compared to a 4-bit binary multiplier, the temporal decimal multiplier reduces the pin count by three-times and area by 40%, simplifying design. The efficiency gained from the reduced pin count and area can be particularly beneficial for larger-scale multiplication operations, such as those involved in Fast Fourier Transforms.
DEVELOPMENT STAGE:
System validation in laboratory environment
PRINCIPAL INVESTIGATORS:
Dilip Vasudevan
Georgios Michelogiannakis
IP Status:
Patent pending
OPPORTUNITIES:
Available for licensing or collaborative research