APPLICATIONS OF TECHNOLOGY:
Applications that relate to advanced semiconductor fabrication, such as:
- Advanced lithography for advanced semiconductor devices, such as for sub-5 nm node chips
- High density interconnects for advanced microelectronic devices
- Faster growth in a single deposition cycle compared to other methods
- Minimal to no lateral growth on the desired growth area
- Adaptability in binding to and modifying various substrates
- Self-aligned deposition process
- Potential tunable affinity to different ALD precursors
As semiconductor technology advances, edge placement error (EPE) becomes a critical barrier in the scaling of semiconductor devices. These errors can lead to misalignment between different layers of the semiconductor device, affecting the functionality and performance of integrated circuits. Using bottom-up fabrication by area-selective deposition, which uses surface modification to block or promote material growth is a viable method to reduce EPEs, but existing molecules used in surface modification do not exhibit enough contrast for high-selectivity deposition. Area selective deposition methods that can reliably reduce EPEs are needed to enhance the performance of semiconductor devices.
Berkeley lab researchers have developed a new method of area-selective deposition based on polypeptoids, a type of bioinspired, sequence-defined polymers. These polymers offer precise control over their chemical composition and properties.
Advantages of this method include significantly faster growth with minimum lateral growth in the desired growth area as it uses an infiltration process, and versatility in adapting to different substrate materials by changing the chemistry of the anchoring group on one end of the polymer chain. This method can also potentially achieve area-selective deposition of mixed metals/metal oxides due to the tunability of monomer chemistry in the sequence-defined polymers on the monomer level, which enables applications for device integration, nanofabrication, and other applications involving complex structure formation.
This invention is expected to be useful for semiconductor manufacturing companies, especially as a self-aligned fabrication process with reduced EPEs in the alignment of features in multilayer device stacks.
Proof of concept
Available for licensing or collaborative research